Uppsala researchers propose streaming LLM weights through spooled fiber instead of HBM. The design is a sketch; the DRAM market that provoked it is very real.
Four computer architects at Uppsala University want to know whether an AI cluster needs local DRAM for model weights at all, or whether 14,000 kilometers of spooled fiber can hold them instead, in flight, as light. Their paper, posted to arXiv on July 9, 2026 under the title "Who Needs DRAM? We Have Fiber," proposes an architecture they call Fiber Memory: a recirculating optical loop that broadcasts a large language model's weights past 10,000 accelerators continuously, so no node ever stores its own copy of the model in HBM or DDR.
The paper presents analytical modeling rather than a prototype or a system simulation. Every number in it is analytical, and the authors say so directly, describing the work as "a first-order architectural feasibility study and a call for further study, rather than a finalized implementation blueprint." That candor is to their credit, and it sets the terms for reading what follows.
It also raises a question: why would a credible computer-architecture group (the senior author, Stefanos Kaxiras, is a professor of computer architecture at Uppsala) spend its effort reviving the delay line, the oldest memory architecture in electronic computing, at data-center scale? The answer sits in the memory market. DRAM contract prices nearly doubled in the first quarter of 2026 and kept climbing through the second. The paper's motivation section cites "rising pressure on DRAM availability and contract pricing," and that pressure is now severe enough that storing model weights in fourteen thousand kilometers of glass reads as a proposal worth costing out rather than a thought experiment. The component physics it leans on deserves a serious look. So does what this paper's existence says about the substrate the field is standing on.
Light in silica fiber travels at roughly 200,000 kilometers per second, so a strand of fiber is also a storage medium: whatever is propagating through it is, for that moment, remembered. Fiber Memory scales that observation up. The design wraps a cluster in 14 parallel fiber links, each built from 20 cascaded 50-kilometer commercial spools into a 1,000-kilometer loop with a 5-millisecond circulation time. Each link is 19-core multi-core fiber, for 266 cores in total (256 active, 10 hot spares), and each core carries eight O-band DWDM channels at 100 Gb/s. That works out, in the authors' arithmetic, to 25.6 TB/s of aggregate loop bandwidth, which at a 5 ms loop delay means 128 GB of data continuously in flight.
The 128 GB budget covers the paper's single worked example: Llama-3-70B quantized to INT8, a 70 GB model, with the remaining capacity consumed by timing slack and interleaved replica layers, overhead the authors put at up to 45 percent of the loop. Each accelerator taps 32 cores and receives 3.2 TB/s, a figure the paper sets beside the 3.35 TB/s an Nvidia H100 SXM draws from its HBM3. The spectral plan is deliberately conservative: eight DWDM channels in a 700 GHz window centered near 1312 nm, the zero-dispersion point of standard fiber, so plain intensity-modulated PAM4 works without coherent DSP.
The rest of the machinery, as the authors describe it, runs like this. A single central weights server holds the model in non-volatile memory, unrolls the matrices to match the accelerators' systolic-array layout, and modulates 2,048 lasers. Each chassis takes a passive 1:99 optical tap, sending one percent of the light to its receivers and passing 99 percent onward. Loop losses are recovered by praseodymium-doped fluoride fiber amplifiers (PDFAs), the niche amplifier family that works in the O-band, plus an all-optical 2R regenerator per cable in every pod to keep the signal above the PAM4 detection threshold; the authors note this regeneration is required, not optional. On the receive side, the design assumes co-packaged optics in its strongest form: photonic ICs on the same interposer as the compute silicon, with 256 micro-ring resonators per accelerator demultiplexing weight streams directly into systolic-array registers. Weights never touch DRAM. Activations and the KV cache still live in local memory; Fiber Memory removes the model copy, not the node's memory system.
One property follows from the physics and cannot be engineered away. A node that misses a weight packet waits for it to come around again, up to a full 5 milliseconds. More on that below.
The paper's headline number is about energy. By the authors' accounting, delivering weights to 10,000 accelerators from per-node HBM3e at 4.0 pJ/bit costs 1,024 kW, while the fiber loop (lasers, trunk and pod amplifiers, regenerators, receivers) costs 284.8 kW. That is the source of the 72.1 percent reduction figure, alongside the elimination of roughly 700 TB of replicated HBM3e capacity across the cluster. Every term in that comparison is a paper calculation. Nothing has been measured, because nothing has been built.
The arithmetic checks out internally; the foundations are softer. The dominant fiber-side term, 179.2 kW for the receivers, is 63 percent of the total, and it extrapolates a 0.7 pJ/bit figure from a 2021 journal paper describing a 16 Gb/s receiver in 65 nm CMOS up to 50 Gbaud PAM4 with clock recovery, equalization, and FEC decode at 25.6 Tb/s per chassis. The tally excludes the weights server, which modulates 2,048 lasers at 100 Gb/s each, and the cooling load of a distributed amplifier fleet. The HBM baseline has its own tilt: it assumes continuous peak-bandwidth fetch, which inflates it, while omitting refresh and static leakage, which deflates it. The authors call that trade conservatively balanced, and they are transparent about the assumptions. A fair reading is that the direction is plausible and the magnitude untested.
Delay-line memory is where electronic computing started keeping its thoughts. Bits were stored as acoustic pulses circulating through tubes of mercury, read at the far end and rewritten at the front. Cambridge's EDSAC ran on mercury delay lines in 1949. UNIVAC I shipped them commercially in 1951, and cheaper magnetostrictive wire lines survived in desktop calculators into the 1970s, until semiconductor RAM ended the category (delay-line memory history, the same lineage the authors invoke themselves). The defining trait then is the defining trait now: no random access. You wait for your bit to come around.
Nor is the optical version new. Researchers built small fiber-optic delay-line memories in the early 1990s (Applied Optics, 1990; 1992), and the concept was patented in 1991. The idea has sat at lab scale for 35 years. What changed is the confluence around it: co-packaged optics entering volume production, multi-core fiber setting petabit transmission records, and a DRAM market painful enough to make the question commercially interesting. That confluence is the story.
The memory market of mid-2026 supplies the motivation the paper only gestures at. Conventional DRAM contract prices rose roughly 93 to 98 percent quarter over quarter in Q1 2026, and industry revenue jumped 81 percent in a single quarter to a record. TrendForce projected another 58 to 63 percent increase for Q2 as cloud providers locked in long-term agreements. SK hynix has reported its entire 2026 HBM output already spoken for (NAND Research), and every HBM wafer start compresses commodity DRAM supply; by that same reading, a roughly 3:1 wafer trade-off separates HBM from standard DDR5. The squeeze reaches far enough down the stack that TrendForce estimated DDR2 contract prices would rise 55 to 60 percent in Q2, followed by another 35 to 40 percent in Q3.
Supercomputing News has tracked this reorganization from two directions: the memory supply chain rearranging itself around data-center AI at the consumer end, and HBM allocation, not supply, becoming the binding constraint at the infrastructure end.
Against that backdrop, Fiber Memory is the most radical entry yet in the taxonomy of HBM alternatives that runs through CXL pooling and processing-near-memory, and it shares a premise with the more grounded ones: memory should be a system-level resource rather than a per-chip one, the same logic behind d-Matrix's bet that inference is a systems problem. The funding line deserves one clause: this is Swedish public research money, via a Swedish Foundation for Strategic Research grant, probing a supply problem created by hyperscale demand that no university can buy its way around.
The paper's best-supported assumption is the optics. TSMC's COUPE silicon photonics platform entered production this year, per industry reports; Broadcom's Tomahawk 6 "Davisson" CPO switch is shipping at 102.4 Tb/s; Nvidia has announced Quantum-X Photonics, with early hardware appearing through partners, while broader photonics-switch availability stays staged through 2026. Every one of those is switch-side CPO. As we argued when we mapped co-packaged optics' two front doors, the compute-side door, photonics on the accelerator package feeding data into the chip itself, has not opened commercially. Fiber Memory assumes photonic receivers demuxing straight into register files, a step beyond anything on a public accelerator roadmap.
The supply chain is the bluntest problem. The design needs 14,000 kilometers of 19-core multi-core fiber as commodity spools. Nineteen-core fiber is record-setting laboratory technology: NICT and Sumitomo Electric pushed 1.02 petabits per second through 1,808 km of it in 2025. What has shipped commercially is 2-core fiber in Google's subsea cables and the 4-core MCF underpinning a 192-core submarine cable system from NTT. No public price exists for 19-core fiber at any volume. The amplifiers are scarcer still. By our reading of the paper's own deployment rules, one loop needs roughly 3,780 PDFAs, and O-band PDFAs remain a narrow specialty market, with products listed by vendors such as FiberLabs and Thorlabs rather than a commodity amplifier ecosystem.
The workload fit is the deeper problem. Broadcasting every weight past every node every 5 milliseconds is the right shape for dense models, where each token touches the full parameter set. Many of 2026's leading open-weight contenders are sparse mixture-of-experts models. DeepSeek V4, GLM-5.2, and Kimi K2.6 all ship open-weight MoE, and independent benchmarks place them near the frontier. In an MoE each token activates a fraction of the parameters, so a full-model broadcast delivers mostly weights nobody asked for. The paper's supporting statistic, that weights consume 90 to 99 percent of inference memory bandwidth, comes from dense-model, small-batch serving circa 2022; under large-batch, long-context workloads the KV cache, which Fiber Memory explicitly keeps local, becomes the bandwidth hog. Dense-model broadcast inference does still exist at scale, and immutable-weight broadcast is genuinely elegant for it. But the paper's chosen case study is its friendliest possible workload, and the field is moving the other way.
Then there is the access model. A circulating loop is sequential by physics. HBM answers a random read in about 100 nanoseconds; a node that misses its layer here stalls for up to 5 milliseconds, and the whole cluster's decode cadence is capped by the loop period. Continuous batching and speculative decoding, the standard 2026 serving stack, assume the accelerator decides when to read weights. In this architecture the fiber decides, and the mitigations the authors propose already burn 45 percent of loop capacity in their own example. Capacity scaling is unforgiving too: by the paper's ratios, a 1-trillion-parameter INT8 model needs on the order of 100,000 kilometers of 19-core fiber and tens of thousands of amplifiers, per model, while HBM density improves every generation. And a single loop fed by a single weights server puts 10,000 accelerators behind one trunk cable and one transmitter. The hot-spare cores cover fiber-core failures; a cable cut idles the whole cluster, and the paper offers no loop-level redundancy story. Anything that mutates weights in flight, fine-tuning included, sits on the future-work list, which fences the design out of training entirely.
What the skepticism should concede: the component-level physics the paper cites is sound and well-documented. O-band dispersion behavior, PDFA gain dynamics, tap losses, micro-ring demux, and the error tolerance of quantized weights are all established results the paper draws on, and nothing in it violates physics. What stays unproven is whether the whole thing holds together at scale. The gaps are systems integration, supply chain, and workload fit, which is what "first-order feasibility study" means, and the authors never pretend otherwise. The one number the paper conspicuously lacks is cost. For a proposal motivated by DRAM pricing, there is no capex analysis, and none is possible with public data, because the exotic components have no public prices. That absence is itself a finding.
The substrate question this pillar keeps asking, most recently of thermodynamic computing's first silicon, is which frontier architectures cross into the foundation of the supercomputing stack and which stall as interesting research. On the evidence of its own pages, Fiber Memory sits far out on the frontier: unbuilt, unsimulated, dependent on unpurchasable fiber and a receive path no accelerator vendor has committed to, and aimed at a workload shape the frontier is abandoning. The paper was posted to arXiv on July 9, 2026, unrefereed, and not yet subjected to broad community scrutiny.
Read it instead as a barometer. When contract DRAM nearly doubles in a quarter, the field starts costing out alternatives that would have been unpublishable five years ago, and an established architecture group now finds it worthwhile to ask, in public and with straight-faced arithmetic, whether the speed of light in glass can substitute for a memory controller. The authors close by asking for follow-up work: simulation, synchronization protocols, an answer on whether the ring can carry ordinary traffic. Whether anyone funds it will depend less on the elegance of the loop than on where the DRAM contract price sits when the next quarter's numbers land.
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