At Computex 2026, Wiwynn and eight ecosystem partners showed a full optical scale-up rack built around compute-side optics. It is a useful moment to separate two technologies the supercomputing industry keeps filing under one acronym.
When Nvidia put co-packaged optics inside its switches earlier this year, the industry started treating CPO as a settled story: optics move onto the package, copper retires, the AI supercomputer keeps scaling. The framing is half right. Co-packaged optics is not one technology with one destination. It has two, and they solve different problems at different points in the machine.
One puts optics next to the switch ASIC. The other puts optics next to the compute die. Both are real, both are shipping or close to it, and only compute-side optical I/O directly addresses the accelerator package-to-first-hop electrical path that has become the hard constraint on scale-up.
That distinction is what made the demonstration at Computex 2026 worth a second look.
On the show floor, ODM Wiwynn and a set of named partners showed a rack-scale optical scale-up system, presented as a full-stack path from chip-level CPO to data-center-scale deployment. The component list, per the partners' announcement: an AI ASIC integrated with optical I/O in a co-packaged configuration, Ayar Labs TeraPHY optical engines, Ayar's ELSFP SuperNova external light sources, in-chassis fiber routing, and a Wiwynn liquid-cooling loop built specifically to keep the external laser stable. The named partners were Ayar Labs, Global Unichip Corporation (GUC), Browave, Corning, FOCI, Molex, SENKO, and TE Connectivity.
The AI ASIC was not named. The announcement describes the chip only as an AI ASIC in a 2.5D package, with no SKU. It's important to note, this was a partner ecosystem demonstration, not a product launch by any single vendor. Ayar Labs is one of eight companies on the list, supplying the optical I/O path.
What the demo does show is harder to get and more interesting than a product launch: an open, multi-vendor optical scale-up architecture assembled from merchant parts. It extends the 1,024-accelerator rack-scale reference design that Ayar and Wiwynn first revealed at OFC in March, which the two showed then only in private briefings. The signal at Computex is the wider cast: the same scale-up architecture, now surrounded by eight named suppliers and shown in public rather than as a two-party preview.
Here is the distinction the single-bucket CPO coverage tends to flatten.
Switch-side CPO co-packages the optics with the switch ASIC. This is what Nvidia has brought to market first on the InfiniBand side with Quantum-X Photonics, while Spectrum-X Ethernet Photonics is slated for broader availability in the second half of 2026. Either way, the optical engines move onto the switch package instead of relying on a faceplate full of pluggable transceivers. Broadcom's third-generation Tomahawk 6 CPO ("Davisson") takes the same architectural position from the merchant-switch side. Switch-side CPO attacks the scale-out fabric: switch power, port density, and the reliability tax of thousands of pluggable modules.
Switch-side CPO leaves the first hop untouched. Between the GPU package and that first-hop switch, the link is still electrical. Copper still carries the signal off the accelerator.
Compute-side optical I/O moves the optics onto or beside the XPU package itself. The optical engine sits at the edge of the compute die, so the signal converts to light before it leaves the package. This is the architecture in the Wiwynn rack, and it is the one that removes the copper segment switch-side CPO leaves in place. The merchant ecosystem is targeting ramp-to-volume for hyperscaler deployments around 2027. It is not in broad production today.
The reason the two are not interchangeable comes down to which bottleneck each one relieves.
Scale-up and scale-out look like the same engineering problem at two sizes. They are not.
Scale-out connects nodes across the fabric. Scale-up connects accelerators inside a tightly coupled domain, where they behave as close to a single large machine as the interconnect allows. By Ayar Labs' own framing, scale-up is the larger challenge, "requiring at least 10x the bandwidth and 10x latency reduction" relative to scale-out. The company's position is direct: "Breaking through these AI performance barriers requires integrating CPO directly into the GPU package." Read that as a vendor making the case for its own category. It also happens to describe the physics.
The physics is copper at the edge of the die. As per-lane rates climb toward 200 Gb/s, the electrical path off the package gets expensive fast. Nvidia's own number, from its engineering write-up on co-packaged optics, is stark: a traditional pluggable path can incur up to 22 dB of electrical loss for a 200 Gb/s channel, against roughly 4 dB once the optics move onto the package. That loss has to be recovered, which means DSP, retimers, and SerDes burning power and throwing heat right where the accelerator can least afford it. In the same write-up, Nvidia attributes a 3.5x power-efficiency gain and a 10x resiliency improvement to its co-packaged switch design. (Nvidia's silicon photonics product page cites different figures for a different configuration; the numbers do not transfer between sources, so they are kept separate here.)
This is the copper wall the optical-interconnect thesis has been pointing at for two years. We have covered the argument that copper runs out of room before the accelerators do, and Nvidia's component bets on optical I/O were an early tell that the largest vendor in the field agreed. Switch-side CPO is the answer to that wall at the fabric. Compute-side optical I/O is the answer at the package. A rack can need both, and the Wiwynn system is one attempt to show what the package-side half looks like in hardware.
The optical engine in the rack is Ayar's TeraPHY, a UCIe-compatible optical I/O chiplet. In its third generation Ayar rates it at 8 Tbps bidirectional. Because it speaks UCIe in streaming raw mode, it is protocol-agnostic at the package boundary: it can carry NVLink, CXL, UALink, or Ethernet without caring which. Ayar cites a path to more than 100 Tbps of optical I/O per accelerator at the package. That figure is the company's, not an independent benchmark, and should be read as a roadmap claim rather than a measured result.
The laser is the part most worth watching, because it is where the rack's thermal and reliability story lives. Ayar's design keeps the laser outside the package. The SuperNova source is delivered as an ELSFP, an External Laser Small Form-factor Pluggable module, feeding light into the TeraPHY engines over fiber. Keeping the laser off the hot compute die is the whole point: lasers are the temperature-sensitive, failure-prone element in any optical link, and putting one next to an accelerator running at full tilt is asking for trouble.
That is the part of the demo the cooling people should care about. Wiwynn built a dedicated liquid-cooling loop just for the ELSFP light source. Not the ASIC, the laser. As optical I/O moves onto compute packages, the external light source becomes its own thermal domain with its own cooling budget, and the rack has to account for it separately from the parts everyone already knows how to cool. It is a small detail that points at a real infrastructure shift: the laser plant is now a managed subsystem inside the rack, not a component you forget about.
Step back from the demo and the strategic picture is a fork.
One road is vertical integration. Nvidia owns the switch ASIC, the CPO, the GPU, and NVLink. Its optics are not sold to anyone else. If you buy into that stack, you buy the whole stack, and the optical interconnect comes as part of the system rather than as a part you can source.
The other road is the merchant, open-standards path, and it is where Ayar sits. TeraPHY is a merchant optical I/O chiplet built on the open UCIe-Optical specification, fabbed on GlobalFoundries' Fotonix process, and designed to be integrated by ASIC houses such as GUC into someone else's XPU or switch package. The bet is that an open optical I/O layer becomes infrastructure the way PCIe or Ethernet did, available to every accelerator designer who does not own a captive optics group. It is a different bet from the more closed architectures pursued by Lightmatter's Passage, and from Celestial AI's Photonic Fabric. Marvell announced a definitive agreement in December 2025 to acquire Celestial AI. This same consolidation dynamic has been reshaping the fiber-interface layer, where incumbents have moved fast to lock down connector and fiber-routing supply.
Where Ayar can fairly claim a lead is in the open lane. It shipped the first UCIe-Optical chiplet in production volume at OFC in 2025, and it carries an unusual investor roster for a single company: Nvidia, AMD, Intel Capital, and MediaTek all hold stakes, which is about as broad a cross-vendor alignment as exists in the category. The Wiwynn rack is a real, demonstrable design win for that merchant path.
It is not volume, though. The honest read on the whole field, Ayar included, is that there is no publicly confirmed, named hyperscaler design-in for compute-side CPO in an AI accelerator at volume right now, for any vendor. Best public sourcing has Ayar progressing toward volume manufacturing and positioning for 2027 deployments, not shipping at scale today.
The most prominent claimed hyperscaler design-in for compute-side CPO is the Marvell-Celestial AI link to AWS Trainium, and it is analyst inference, not a disclosed design-in. It traces to a Marvell 8-K dated December 2, 2025 that issued Amazon warrants tied to purchases of photonic fabric products through 2030, paired with a Celestial statement about "a major hyperscaler." Neither Marvell nor Amazon named AWS Trainium as the platform. The inference is reasonable. It is still an inference, and it should not be repeated as a confirmed design-in.
It is worth separating that from the louder optics story of the same stretch. Nvidia spent the spring buying into the optical supply chain: $2 billion each into Lumentum, Coherent, and Marvell, plus a separate Corning manufacturing partnership, and a slot in Ayar Labs' $500 million Series E. That is real money and a real signal. It is also a different category, a merchant accelerator vendor securing optical components and capacity, much of it feeding its own networking roadmap, rather than a hyperscaler committing to a compute-side CPO accelerator. Supply-chain investment is not a design-in, and the two get cited as if they were.
Broadcom's Tomahawk 6-Davisson is the most concrete merchant switch-side CPO product disclosed publicly, though Broadcom's own availability language points to sampling/early-access status, and Broadcom has not disclosed a named XPU pairing either. So the accurate state of play is this: switch-side CPO is shipping or sampling from named vendors; compute-side optical I/O is demonstrable at rack scale and progressing toward volume; and the named, at-scale hyperscaler accelerator design-in that would settle the argument has not been publicly confirmed for anyone.
The Wiwynn showcase does not change that, and on its own it is not a turning point. It is one more step in a steady ramp: a two-party reference design under private briefing at OFC in March, the same architecture out in public with eight named suppliers by June. For a substrate technology trying to cross from frontier to foundation, the slope is what to watch, not any single demo. How fast does the open, multi-vendor path fill in quarter by quarter, and does a named hyperscaler design-in ever land to settle the argument.
For practitioners, the working question is narrower than "is CPO ready." It is which door a given announcement walked through. A switch-side part relieves the scale-out fabric and leaves the first hop on copper. A compute-side part goes after that first hop directly. The two get filed under the same acronym, and they answer different questions about how large a single coherent AI machine can get.
