July brought integrated cryogenic control and new process-development commitments. HRL's chip can host 18 qubits, but its largest published circuit used seven.
On July 22, Japan's New Energy and Industrial Technology Development Organization selected Hitachi as the prospective implementing organization for a silicon quantum project jointly proposed with Intel K.K. and to be pursued with AIST. The program plans to use Intel 18A process technology and targets prototypes implementing quantum error-correcting codes at the 100-qubit scale in fiscal 2028 and the 1,000-qubit scale in fiscal 2030.
One day later, IBM signed a definitive agreement to acquire HRL Laboratories, the research lab jointly owned by Boeing and General Motors. Terms were not disclosed, and IBM expects the transaction to close by the end of the third quarter, subject to customary conditions and regulatory approvals. On July 29, Nature published an HRL Laboratories silicon processor under integrated cryogenic control and a QuTech spin-shuttling device that performed weight-four parity checks.
The evidence for manufacturability and integrated control improved within eight days. The announcements did not move the modality to large-scale computation. HRL Laboratories' chip is configurable for up to 18 exchange-only qubits, but the largest circuit reported in the paper used seven. QuTech's experiment used five. Neither paper demonstrates a below-threshold logical qubit, and none of the industrial announcements commits high-volume spin-qubit production.
HRL Laboratories' processor combines a 54-quantum-dot Si/SiGe chip with a 296-line superconducting ribbon cable and a cryogenic CMOS controller at 4 kelvin. Each exchange-only qubit encodes information in three electron spins held in three adjacent quantum dots. Control uses baseband gate-voltage pulses rather than electron-spin-resonance drive.
The qubit chip can be configured for up to 18 qubits. That is architectural capacity, however it’s not the size of a reported computation. The distance-5 repetition-code experiment used seven qubits. The [[4,2,2]] quantum error-detection experiment used six.
The controller was fabricated in a commercial 130-nanometer RF CMOS process and contains about 70 million transistors, 156 output channels and 366 digital-to-analog converters. It generates the time-varying control signals at 4 K, while the qubit chip operates at an average electron temperature near 150 millikelvin. HRL Laboratories fabricated the quantum device with a proprietary 200-millimeter wafer process.
The gate data show an order-of-magnitude improvement over earlier exchange-only results, according to the paper. Mean single-qubit error was 1.7 × 10⁻⁴, equivalent to 99.983% fidelity. Mean two-qubit CNOT error was 3.5 × 10⁻³, or 99.65% fidelity, and the lowest reproducible CNOT error was 9 × 10⁻⁴. Keeping the one-qubit and two-qubit figures separate matters because error-correction circuits depend heavily on the latter.
The two code experiments also need separate labels. The distance-5 repetition code is an error-correction experiment: its reported logical error rate was about 5 × 10⁻³, compared with 2.4 × 10⁻² for the average distance-3 subsets drawn from the same data. The [[4,2,2]] experiment performed quantum error detection. It reached a two-logical-qubit state fidelity of 0.95 after three syndrome-extraction rounds, but only after postselection rejected roughly 77% of the shots. Without using the error-detection measurements, average fidelity was 0.59.
The repetition code tests error suppression, while the error-detection circuit tests postselected logical-state preparation. Neither is a below-threshold logical qubit. SCN's guide to the quantum error-correction code landscape explains why a code experiment, an encoded logical state and below-threshold logical operation make different claims.
QuTech approached the connectivity problem with a mobile ancilla, a helper qubit used to measure the state relationships among data qubits. Its five-qubit silicon device shuttled the ancilla among four data qubits and performed the X-type and Z-type weight-four parity checks used in a surface-code stabilizer.
The ancilla traveled about 1.2 micrometers round trip with reported shuttling fidelity of 97.7%. The complete parity checks reached 72.2% accuracy for Z-type measurements and 67.0% for X-type measurements. The 97.7% transport fidelity does not carry through to the complete parity check. A mobile spin can do useful work during a stabilizer circuit, while the full operation remains well short of a practical surface-code regime.
A July Nature Communications paper from Diraq and imec reports a 300-millimeter foundry-fabricated SiMOS device that coherently controlled and characterized all eight qubits in a linear array. Calibration was organized around four double-dot cells, and the team demonstrated an entangling gate on one adjacent pair rather than across the full array. It is evidence for coherent array control on an industrial process, not an eight-qubit error-correction circuit.
The July announcements do not establish dedicated spin-qubit foundry capacity across three continents. They show several kinds of progress that should remain distinct: peer-reviewed devices from industrial processes, active process-development partnerships, government-funded pilot programs and proposed future facilities.
Europe's SPINS pilot-line program launched in April to develop spin-qubit processes, process design kits and multi-project-wafer infrastructure. External access is planned for a later phase. SCN's earlier coverage of SPINS explains the three technology platforms under development, but the program is not yet an established open-access manufacturing service.
Program | Process/foundry | Evidence level | Hardware demonstrated? |
|---|---|---|---|
HRL Laboratories and IBM | HRL proprietary 200 mm Si/SiGe process; Anderon described as a potential future path | Peer-reviewed hardware plus a proposed manufacturing option | Yes. Architecture supports up to 18 qubits; largest reported code circuit used seven |
300 mm CMOS-compatible SiMOS foundry process | Peer-reviewed hardware | Yes. Eight qubits controlled and characterized; entangling gate on one adjacent pair | |
Intel 18A process planned | NEDO-funded process and system development program | No hardware reported under this program | |
European multi-platform pilot-line development | Publicly funded process, PDK and future access program | No hardware reported by the program at launch | |
300 mm GlobalFoundries 22FDX | Peer-reviewed device work plus a commercial partnership | Yes. A 1,024-quantum-dot array was characterized; it was not a 1,024-qubit processor |
The rows show several leading programs with named industrial fabrication or process-development partners. The arrangements do not reveal production allocation, and Diraq's relationships with both imec and GlobalFoundries show why exclusivity cannot be inferred from a partnership announcement. The US foundry picture remains provisional: IBM says its planned acquisition of HRL Laboratories creates an opportunity for closer work with Anderon, including potential spin-qubit manufacturing, but it has not announced a committed process or production plan. SCN previously examined Anderon and the federal foundry programs in its coverage of the Commerce Department's quantum manufacturing package.
Integrated control makes the HRL Laboratories paper more important, but it also puts a number on the thermal problem. The controller consumes no more than 3.5 watts in typical operation. Dividing that upper figure by the chip's nominal 18-qubit configuration gives a crude allocation of about 194 milliwatts per nominal qubit.
That is not a measured per-qubit power figure, marginal power consumption or a scaling law. The controller has fixed overhead, its 156 channels do not map one-to-one to 18 qubits, and the paper does not report simultaneous operation of 18 qubits.
An arXiv version of a review on spin-qubit CMOS compatibility puts commercial cooling capacity at 4 K between 2 and 4 watts. For a million-qubit system, that implies less than 4 microwatts per qubit and as little as 2 microwatts at the lower end of the cooling range. Comparing those allowances with the crude 194-milliwatt allocation produces an illustrative gap of roughly 49,000× to 97,000×. The comparison is intentionally naive. The review's own survey places most cryogenic control demonstrations about 1,000× above the target and warns that the underlying demonstrations are not directly comparable.
The prototype interconnect conducts less than 10 microwatts from the 4 K stage to the millikelvin stage. That is a low thermal load for this device, but it does not answer million-qubit routing, fan-out or signal-integrity requirements.
CMOS compatibility also stops short of process identity. The review notes that 300-millimeter deposition of isotopically enriched silicon has been demonstrated in research fabs but is not commercially offered. It also explains that valley-splitting requirements differ from the parameters classical CMOS processes were built to control. High transistor or quantum-dot yield therefore does not establish qubit yield, which depends on spin behavior, device variability and control fidelity across a full array.
The Department of Energy's public target calls for fault-tolerant systems with logical-qubit counts in the low hundreds by 2028. NEDO's fiscal-2028 milestone is different: a 100-physical-qubit prototype implementing error-correction codes. Among the public milestones reviewed here, none targets a fault-tolerant silicon-spin system by 2028. SCN's earlier analysis of the DOE quantum target explains why physical-qubit counts and logical performance cannot be compared directly.
The next reports need to resolve the same distinctions. NEDO's prototype needs to disclose how many qubits are calibrated and operated in the reported circuits, along with code performance. SPINS needs external users to fabricate and characterize devices through its shared processes. IBM and Anderon need a committed spin-qubit process roadmap. For HRL Laboratories, the useful next disclosures are active qubits per circuit, two-qubit error distributions under parallel load and controller power per active channel.
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