National labs will run and grade the circuits. No hardware results include the 50 fault-tolerant hard operations due at the prototype stage yet.
On September 17, 2026, the Department of Energy's Office of Science posted the request for applications for the Quantum Genesis Q Competition, DE-FOA-0003657, along with a sample Other Transaction Agreement and a $45 million companion lab call for the testbed that will check the results. According to DOE's announcement, the competition plans up to $215 million for private companies that can demonstrate a fault-tolerant quantum computer with at least 100 logical qubits. The RFA sets the main evaluation for September 2028, and applications are due October 19.
In June, Supercomputing News argued that DOE's 2028 fault-tolerance target turned on a definition the department had not yet written. Executive Order 14413 gave the Secretary of Energy until about September 20 to identify technical specifications and, where appropriate, publish a summary. None of the September 17 documents call themselves that summary, but the RFA is the first DOE document to attach money to the definition. It sets neither a logical error rate nor a code distance. The bar sits in a test instead: circuits specified by a DOE verification team, run on the machine by national laboratory staff, and checked for correctness.
Infleqtion, Quantinuum and IBM each published an error-correction result in the eight days before the RFA posted, each expressed as a ratio or a multiple, and the three do not share a unit. The analysis near the end sets those results, and five vendors' roadmaps, against the September 2028 evaluation.
The RFA defines a logical qubit broadly, as an effective qubit spread across several subsystems and operated under error correction. The sample OTA's version is tighter: a state encoded in an error-corrected subspace of multiple physical qubits, on which logical gates act as they would on an ideal qubit. Neither version carries a number, and neither requires logical qubits to beat the physical qubits they are built from.
The numbers attach to a second term. A hard operation, in DOE's definition, is one that is difficult in the performer's error-correction scheme but needed for universal computation. In the stabilizer codes most vendors use, that means non-Clifford gates such as T or Toffoli: without them, a circuit can be simulated efficiently on a classical computer, and common codes can apply them only through extra procedures such as magic-state preparation. DOE says it will benchmark machines partly by how many hard operations they complete reliably, a count it calls "a test of both the error rate and the stability of the computer."
The prototype milestone in the sample OTA, due about a year in, requires 10 logical qubits held for 1,000 non-trivial logical clock cycles at a fidelity of 1/e, about 37 percent, and circuits over a fully fault-tolerant universal gate set that include at least 50 of the platform's hardest operations. The first-generation milestone asks for circuits on at least 100 logical qubits, specified by the verification and validation (V&V) team and standardized across awardees. Compiled on a reference architecture the OTA does not name, they reach approximately 10^4 to 10^5 hard operations within a space-time volume of 10^8, which the OTA says could vary with advances in architecture. Space-time volume is qubits multiplied by time steps, so 100 logical qubits running for a million logical cycles would be 10^8.
For the first-generation milestone, the V&V team runs the demonstrations itself, and the OTA says it "will assess the correctness of the outputs." Prototype demonstrations run in collaboration with the team. The RFA names national laboratory staff as the verifiers, leaves DOE free to add other neutral third parties, and gives them physical and virtual access to each machine along with permission to operate it.
The exclusion, by contrast, is spelled out. Among applications not of interest, the RFA lists machines that are not fault-tolerant or "are only capable of error mitigation or detection and not correction," even if the applicant believes error rates can reach scientific relevance without fault tolerance. Error mitigation reduces the effect of noise by running a circuit many times and correcting the statistics afterward. Error detection flags corrupted runs so they can be thrown away. Of the three techniques, only correction repairs errors while the computation is running.
Tanner Crowder, who leads quantum information science in DOE's Office of Science, put the intent in plainer terms on a press call for the launch. "Our goal is not to have a bunch of qubits that can't do much," he said, according to FedScoop.
Several things are left open. The methodology for measuring logical error rates, gate fidelities, and circuit width and depth is to be agreed with each selected applicant during negotiation and the first milestone. Neither document states what output fidelity the first-generation circuits must reach, and neither mentions post-selection, the practice of discarding runs in which an error was flagged, so it is unsettled whether discarded shots count against a performer. Architectures that do not map naturally onto a logical-qubit count can negotiate equivalent metrics, at DOE's sole discretion, that would also govern the bonus tiers.
Phase I pays two fixed amounts: $250,000 when DOE approves a performer's V&V plan, about six months in, and $1.25 million for a validated prototype, about a year in. Phase II splits three pools evenly after the September 2028 evaluation: a $100 million general pool among every awardee that demonstrates a first-generation machine and two $50 million bonus pools among those reaching 150 and 200 logical qubits. In the RFA's worked example, four performers clear the first-generation bar, one at 200 logical qubits, one at 150 and two at 100. The first collects $100 million across the three pools, the second $50 million, and the other two $25 million each. DOE expects to select at least three and up to ten applicants, and it does not intend to fund more than one built on the same provider's qubit technology.
Darío Gil, DOE's Under Secretary for Science, told reporters the design gives the competition a "reward function" scaled to what gets demonstrated, because DOE does not know which qubit modalities will get there, Nextgov reported.
All of this is planned funding. DOE's release puts the total at up to $215 million, of which $2.5 million is fiscal 2026 money, and under the RFA both the move to Phase II and the size of each pool depend on future appropriations; DOE may end the awards before Phase II if the money is not there.
Awardees site and operate their own machines, and selection commits DOE to no later purchase, in contrast to the on-premises quantum deployments announced in July in Europe and North America, some of which were purchases. The RFA calls the competition a pillar of the Genesis Mission, which SCN has described as a federation built over DOE's new supercomputers, and requires both milestone machines to come with a software stack that works alongside classical supercomputing.
The 2028 date binds the pools more tightly than it binds entry. DOE will consider applicants that plan to reach the first-generation bar by 2030 if they accept the risk that earlier performers claim the milestone payments first. If nobody clears the bar by September 2028 and DOE judges the intermediate progress sufficient, it may extend the agreements and open the program to new entrants.
DOE's September 17 materials describe the first-generation operations requirement four ways. The press release invites proposals for machines "capable of performing hundreds of millions of fault-tolerant operations." The RFA's program-goals section says thousands of hard fault-tolerant operations; its illustrative Table 1 says 10^5, and the sample OTA, as above, is approximately 10^4 to 10^5 within a space-time volume of 10^8.
The table and the OTA agree, and so does the request for information DOE issued in May, which asked about machines running at least 10^5 hard operations. One possible reconciliation, as SCN reads it, is that the release describes the 10^8 space-time volume, which counts every logical qubit at every time step rather than only hard operations, though 10^8 is one hundred million and the release says hundreds of millions. The program-goals figure sits one to two orders of magnitude below the table. The prototype tier has a similar gap: Table 1 lists 10^3 hard operations, and the OTA milestone requires at least 50. Which figures bind can be sent to DOE at [email protected] until October 6 or at the applicant webinar on September 25 at 1 p.m. Eastern.
On September 14, Infleqtion said it had used an early-access build of NVIDIA's CUDA-Q Logical, which NVIDIA announced the same day, to construct and validate a high-rate code from the quantum low-density parity-check family behind the recent expansion of error correction beyond the surface code. The code, a hypergraph-product simplex construction described in Infleqtion's technical blog, uses 98 physical data qubits to encode 18 logical qubits at distance four, a code rate of 18.4 percent, or about 5.4 data qubits per logical qubit. Infleqtion rounds that to about six and calls it a fivefold improvement in code rate over the surface-code approach used for comparison.
Infleqtion reports no hardware run of the code. The company built and checked the code in software and ran it through a compiler pipeline, taking the distance-four figure from the published construction as claimed rather than re-deriving it. The blog calls the figures "not a hardware resource estimate," because syndrome ancillas, atom movement, scheduling, readout, control, and decoding all sit outside the 18-to-98 ratio, and the company says it is extending the workflow toward physical execution.
Quantinuum's Helix architecture, described in a September 8 blog post and a paper posted September 2, rests on a code that encodes two logical qubits in 20 physical qubits at distance six. The paper says this gives roughly a 3.5-fold reduction in spatial overhead (qubit count) compared with conventional rotated surface codes of comparable distance; the blog does not use that figure. Infleqtion's multiple is a similar comparison, but at a different distance and against a surface-code variant and distance it does not name, so the two cannot be set side by side.
Helix, unlike the Infleqtion code, has run on hardware. On Helios, Quantinuum's 98-qubit trapped-ion system, the paper reports an error of about 4.6 × 10^-5 per logical qubit per error-correction cycle over 20 rounds, with a wide confidence interval of roughly 2 × 10^-5 to 1.1 × 10^-4. Its two-qubit logical Clifford error is about 2.8 × 10^-4, which the blog puts at 4.28 times better than the machine's physical two-qubit figure. Both results beat the matching physical baseline without post-selection. The paper did not inject a magic state; it benchmarked the interface that injection would use, the route to the non-Clifford gates DOE counts as hard operations.
IBM's September 15 blog post describes a continuous path from error mitigation to fault tolerance and argues that what ultimately matters "is not what constitutes a logical qubit, but the size of the circuit you can run with the available error-correcting tools."
The multiple IBM publications that week comes from that line of work. In a preprint posted September 11, IBM researchers combined error detection with first-order probabilistic error cancellation, a mitigation method, to simulate transverse-field Ising dynamics on the ibm_aachen processor, and cut the inferred sampling overhead by up to a factor of 63 relative to probabilistic error cancellation without post-selection. The unit is classical sampling cost, roughly the number of circuit repetitions a mitigation protocol needs, so the 63x is neither a qubit ratio nor an error rate.
Set beside the RFA, the technique falls in the category DOE lists as not of interest: machines capable only of mitigation or detection. That category does not describe IBM's fault-tolerance program. The same post calls fault tolerance IBM's north star and points to Starling, the 2029 machine behind IBM's more-than-$10 billion quantum investment plan, which IBM's June 2025 announcement describes as running 100 million quantum operations on 200 logical qubits. For 2028, IBM's roadmap lists prototyping a complete fault-tolerant instruction set architecture and demonstrating multiple modules and magic-state distillation. IBM and DOE both measure progress by circuits but differ on whether mitigation and detection can supply the circuit size; under the RFA, a machine that relies on them alone would not qualify for the milestones.
This section is SCN analysis. Vendor roadmaps are company claims, and no vendor has said publicly whether it will apply.
Counted by logical qubits alone, three of the public roadmaps reviewed here date 100 or more at or before 2028. IonQ's roadmap lists 800 logical qubits on 10,000 physical qubits in 2027 and 1,600 on 20,000 in 2028, each with a logical-error target below 10^-7. QuEra's roadmap lists Libra, launching in 2028, with 256 logical qubits on more than 10,000 physical qubits and 99.9999 percent logical fidelity. Infleqtion's Form 10-K says its roadmap targets 100 logical qubits by 2028, with a warning that it may not get there on schedule, and its Illinois system, under contract for 2027, is designed to scale past 50 logical qubits toward that goal. IBM's Starling (2029) and Quantinuum's Apollo, which the company's 2024 roadmap places by 2030 on a path it says leads to hundreds of logical qubits, fall after the September 2028 evaluation but inside DOE's 2030 allowance.
Measured by operations, the ordering shifts. DOE specifies its first-generation circuits in hard operations and space-time volume, and the roadmap written in the closest terms is IBM's, with Starling's 100 million operations in 2029. QuEra describes Libra as a megaquop machine, on the order of a million reliable logical operations, and lists a gigaquop successor for 2028 or 2029. Infleqtion's 10-K also sets a megaquop target for 2028.
Neither view settles the success criterion, which may decide more than the count does. The OTA sets 1/e fidelity for the prototype and none for the first-generation tier. If DOE carried the prototype's 1/e standard up to a 10^8 space-time volume, the average error would need to be around 10^-8 per logical qubit per cycle. That figure is SCN arithmetic, and DOE has set no such requirement.
At the prototype tier (10 logical qubits, 1,000 cycles, 1/e), the same arithmetic gives about 10^-4 per logical qubit per cycle. Quantinuum's published Helix memory figure of 4.6 × 10^-5, measured on two logical qubits, sits below that, though the top of its confidence interval does not, and the prototype also requires 50 hard operations on a fully fault-tolerant universal gate set, which that paper did not demonstrate.
The demonstrated record is earlier still, and published logical-qubit counts in the tens mix correction with detection. Quantinuum's Helios launch in November 2025 listed 48 error-corrected logical qubits, benchmarked at state preparation and measurement, alongside 94 error-detected ones. The 64-logical-qubit demonstration IBM's post cites, from a preprint by IBM and University of Chicago researchers, relied on syndrome post-selection. Microsoft and Atom Computing's 24 entangled logical qubits in November 2024 combined error detection with correction of lost atoms, as did the 12 logical qubits Infleqtion reported in September 2025. This is not an exhaustive survey; this review does not assess work such as QuEra and Harvard's logical magic-state experiments or Google's recent error-correction papers.
In the documents reviewed here, three U.S. roadmaps, IonQ's, QuEra's, and Infleqtion's, put 100 or more logical qubits on the calendar by 2028, while Quantinuum, which has the largest published error-corrected count among them, and IBM date their machines to 2030 and 2029. None of the hardware results reviewed includes a circuit with 50 hard operations on a fully fault-tolerant gate set, the prototype requirement that falls due about a year after award. How the count-first and depth-first roadmaps compare will depend on the methodology each performer negotiates after selection and on the output criterion the V&V team attaches to the 100-qubit circuits, and neither has been published.
The RFA's eligibility terms sort the field geographically before any circuit runs. Applicants must be for-profit domestic entities, legally formed and physically operating in the U.S., and a foreign entity needs an explicit written waiver. All capabilities must be built, and all work performed, in the U.S., though a partial waiver can be requested. A majority-U.S.-owned domestic lead entity is a program policy factor, and every application faces a separate, non-appealable research, technology and economic security review.
One of the nearest-term machines sits outside those terms as built. Magne, the roughly 50-logical-qubit neutral-atom system with availability listed for early 2027, is being built by Atom Computing with Microsoft software and will be based in Copenhagen, and the Novo Nordisk Foundation says it will be 100 percent Danish-owned. The terms run in the same direction as Commerce's $2 billion in quantum letters of intent and the four CHIPS quantum awards that finalized some of them in September, all pointing federal money at domestic manufacturing.
Full proposals for the V&V lab call are due November 10, three weeks after competition applications close on October 19, so the teams that will check the machines are chosen after the machine proposals are in. Competition selections come no earlier than November 13. After that, the documents that settle what the RFA leaves open are the negotiated V&V plans, due about six months into each award, and the fiscal 2027 appropriations that decide whether the Phase II pools exist at their stated size.
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